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YosysHQ Yosys 0.48-dev documentation
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  • Yosys (index)
  • What is Yosys
  • Getting started with Yosys
    • Installation
    • Synthesis starter
    • Scripting in Yosys
  • Using Yosys (advanced)
    • Synthesis in detail
      • Synth commands
      • Converting process blocks
      • FSM handling
      • Memory handling
      • Optimization passes
      • Technology mapping
      • The extract pass
      • The ABC toolbox
      • Mapping to cell libraries
    • More scripting
      • Loading a design
      • Selections
      • Interactive design investigation
      • Symbolic model checking
  • Yosys internals
    • Internal flow
      • Flow overview
      • Control and data flow
      • The Verilog and AST frontends
    • Internal formats
      • The RTL Intermediate Language (RTLIL)
    • Working with the Yosys codebase
      • Writing extensions
      • Compiling with Verific library
      • Writing a new backend using FunctionalIR
      • Contributing to Yosys
      • Testing Yosys
    • Techmap by example
    • Notes on Verilog support in Yosys
    • Hashing and associative data structures in Yosys

Appendix

  • A primer on digital circuit synthesis
  • RTLIL text representation
  • Auxiliary libraries
  • Auxiliary programs
  • Literature references
  • Internal cell library
    • Word-level cells
      • Unary operators
      • Binary operators
      • Multiplexers
      • Registers
      • Memories
      • Finite state machines
      • Coarse arithmetics
      • Arbitrary logic functions
      • Specify rules
      • Formal verification cells
      • Debugging cells
      • Wire cells
    • Gate-level cells
      • Combinatorial cells (simple)
      • Combinatorial cells (combined)
      • Flip-flop cells
      • Latch cells
      • Other gate-level cells
    • Cell properties
  • Command line reference
    • Yosys environment variables
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