Combinatorial cells (combined)

These cells combine two or more combinatorial cells (simple) into a single cell.

Table 8 Cell types for gate level combinatorial cells (combined)

Verilog	Cell Type
Y = A & ~B	$_ANDNOT_
Y = A | ~B	$_ORNOT_
Y = ~((A & B) | C)	$_AOI3_
Y = ~((A | B) & C)	$_OAI3_
Y = ~((A & B) | (C & D))	$_AOI4_
Y = ~((A | B) & (C | D))	$_OAI4_
Y = ~(S ? B : A)	$_NMUX_
(see below)	$_MUX4_
(see below)	$_MUX8_
(see below)	$_MUX16_

The $_MUX4_, $_MUX8_ and $_MUX16_ cells are used to model wide muxes, and correspond to the following Verilog code:

// $_MUX4_
assign Y = T ? (S ? D : C) :
               (S ? B : A);
// $_MUX8_
assign Y = U ? T ? (S ? H : G) :
                   (S ? F : E) :
               T ? (S ? D : C) :
                   (S ? B : A);
// $_MUX16_
assign Y = V ? U ? T ? (S ? P : O) :
                       (S ? N : M) :
                   T ? (S ? L : K) :
                       (S ? J : I) :
               U ? T ? (S ? H : G) :
                       (S ? F : E) :
                   T ? (S ? D : C) :
                       (S ? B : A);