verific - load Verilog and VHDL designs using Verific

yosys> help verific

verific [-work <libname>] {-sv|-vhdl|...} <hdl-file>

Load the specified Verilog/SystemVerilog/VHDL file into the specified library.
(default library when -work is not present: "work")


    verific [-L <libname>] {-sv|-vhdl|...} <hdl-file>

Look up external definitions in the specified library.
(-L may be used more than once)


    verific -set-error <msg_id>..
    verific -set-warning <msg_id>..
    verific -set-info <msg_id>..
    verific -set-ignore <msg_id>..

Set message severity. <msg_id> is the string in square brackets when a message
is printed, such as VERI-1209.
Also errors, warnings, infos and comments could be used to set new severity for
all messages of certain type.


    verific -import [options] <top>..

Elaborate the design for the specified top modules or configurations, import to
Yosys and reset the internal state of Verific.

Import options:

  -all
    Elaborate all modules, not just the hierarchy below the given top
    modules. With this option the list of modules to import is optional.

  -gates
    Create a gate-level netlist.

  -flatten
    Flatten the design in Verific before importing.

  -extnets
    Resolve references to external nets by adding module ports as needed.

  -no-split-complex-ports
    Complex ports (structs or arrays) are not split and remain packed as a single port.

  -fullinit
    Keep all register initializations, even those for non-FF registers.

  -cells
    Import all cell definitions from Verific loaded libraries even if they are
    unused in design. Useful with "-edif" and "-liberty" option.

  -chparam name value
    Elaborate the specified top modules (all modules when -all given) using
    this parameter value. Modules on which this parameter does not exist will
    cause Verific to produce a VERI-1928 or VHDL-1676 message. This option
    can be specified multiple times to override multiple parameters.
    String values must be passed in double quotes (").

  -v, -vv
    Verbose log messages. (-vv is even more verbose than -v.)

  -pp <filename>
    Pretty print design after elaboration to specified file.

The following additional import options are useful for debugging the Verific
bindings (for Yosys and/or Verific developers):

  -k
    Keep going after an unsupported verific primitive is found. The
    unsupported primitive is added as blockbox module to the design.
    This will also add all SVA related cells to the design parallel to
    the checker logic inferred by it.

  -V
    Import Verific netlist as-is without translating to Yosys cell types.

  -n
    Keep all Verific names on instances and nets. By default only
    user-declared names are preserved.

  -d <dump_file>
    Dump the Verific netlist as a verilog file.


    verific [-work <libname>] -pp [options] <filename> [<module>]..

Pretty print design (or just module) to the specified file from the
specified library. (default library when -work is not present: "work")

Pretty print options:

  -verilog
    Save output for Verilog/SystemVerilog design modules (default).

  -vhdl
    Save output for VHDL design units.


    verific -cfg [<name> [<value>]]

Get/set Verific runtime flags.


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